1. Field of the Invention
The present invention relates to a semiconductor memory device having a built-in high-speed read/write shift register of a capacity corresponding to a group of memory cells on a word line and, more particularly, to a device directed to enabling one-bit shift in write transfer operation and driving a divided shift register.
2. Description of the Related Art
In the related art, there are known semiconductor memory devices which have a random access memory (RAM) and a shift register that can parallel-transfer data for a group of memory cells on a word line, thus enabling high-speed read/write operations. The semiconductor memory devices are utilized advantageously for image processing and the like, e.g., for use as video RAM's (VRAM's).
In one prior art VRAM, stages of a shift register are arranged in two columns; one for odd numbered bit lines and one for even numbered bit lines. An input side multiplexer allots serial data input S(in) alternately to the odd column and even column bit by bit. An output side multiplexer combines the odd column outputs and the even column outputs to form a serial data output. Internal clocks, equivalent to one cycle of a shift clock, are used. Thus, two cycles of a shift clock are needed for a one-bit shift in the two columns. On the other hand, changes in the output data after combination by the output multiplexer correspond to one cycle of the shift clock.
Thus, the rate of data transfer between the odd column and the even column is one-half that of the external input data and the external output data. This means a low-speed shift register is appropriate. Alternatively, if a normal speed shift register is used, it is possible to double the bit rate of the external input/output data and, thus, to achieve high-speed RAM write/read operations.
In the odd and even shift register columns, since two cylces of a shift clock are used for a bit shift, if a parallel data write-in operation is performed on a RAM for each cycle of the shift clock, then, while a prior stage of data (Q.sub.N-1) is in a master stage, the output (Q.sub.N) of the slave stage will be transferred to the RAM even if the output is the same as before or if the slave stage is in the process of changing and the output is still not settled.
It has been proposed to parallel transfer data to the RAM after the completion of a shift operation. In this case, there is the problem in that the odd column can only be connected to odd numbered bit lines, and the even column can only be connected to even numbered bit lines. Due to this, a two-bit shift can be executed, but not a one-bit shift. If parallel data transfer were performed per each shift clock, e.g., if word line selection were performed in the order n-th, (n+1)-th, (n+2)-th, and so on, the display screen of the apparatus incorporating the VRAM would show the same pattern of horizontal lines shifted by one bit. This type of processing may sometimes be required for image processing, but division of a shift register into odd numbered stages and even numbered stages would, again, limit such processing to two-bit units.